IEEE Sensors Council Gujarat Section

IEEE Sensors Council Gujarat Section

IEEE Sensors Council Gujarat Section

Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor for Low-Voltage Low-Power Analog and Digital Circuits

Abstract: In recent times, as the device length has substantially decreased, novel doping techniques are required for developing concentration gradient at the junctions. The primary advantage of JunctionLess device is the simplicity in fabrication process. The main difference between a JunctionLess (JL) transistor and a classical MOSFET is the absence of junctions i.e. uniform doping for the entire length of the device. The device is heavily doped and the doping is of the order of 1018 to 1019 cm-3. In JL transistor, bulk conduction takes place in contrast with the surface channel conduction in classical MOSFET. In sub-threshold region, JL transistor is fully depleted. As the gate voltage approaches threshold voltage, it becomes partially depleted and when it reaches flat-band voltage, it is fully on. In sub-threshold region, due to depletion, electric field in JL transistor is very high and above threshold, electric field reduces. This is in contrast to Inversion-Mode (IM) MOSFET where electric field is low in sub-threshold region and high after threshold voltage. As the current flow is mainly concentrated at the centre of film, surface scattering is very less which increases mobility and hence current drive in JL transistor. Single Material Double Gate (SMDG) has several advantages as mentioned above but there are some drawbacks due to high doping concentration. It reduces mobility of the carrier which in turn affects drive current and trans-conductance. The above problems can be avoided by using Dual Material Double Gate (DMDG) JL transistor. DMDG has two metals in two gates having different work functions. Due to different gate materials, potential step profile is created which screens the effect of drain potential variation. Due to this, several advantages like high on-state current, improved trans-conductance and reduced DIBL are observed. These effects have been investigated by developing efficient drain current model for DMDG JL transistor using conformal mapping technique.

April 14, 2017

Speaker: Manoj Saxena

Affiliation: DL and Regional Editor of IEEE EDS south Asia

Venue: DA-IICT, Gandhinagar

Bio: Manoj Saxena is currently Associate Professor in Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India. He received B.Sc. (with honors), M. Sc., and Ph.D. degrees from the University of Delhi in 1998, 2000, and 2006 respectively. He has authored or coauthored 210 technical papers in international journals and various international and national conferences. His current research interests are in the areas of analytical modeling, design, and simulation of non classical MOSFET architectures like silicon-on-nothing, insulated-shallow-extension, grooved/concave-gate, cylindrical gate and Tunnel FET. He is reviewer to many journals including Solid State Electronics, Journal of Physics: D Applied Physics and IEEE TED and EDL. He is Senior Member of IEEE and also Member of Institute of Physics (UK), Institution of Engineering and Technology (UK), National Academy of Sciences India (NASI), Associate of Indian Academy of Sciences, Bangalore member of International Association of Engineers (Hong Kong). Currently, he is Regional Editor for South Asia, IEEE EDS Newsletter; IEEE Electron Device Society-Region 10 SRC Vice Chair and EDS Distinguished Lecturer and Fellow-IETE, India. For his voluntary contribution, he has received the outstanding EDS Volunteer recognition from EDS Chapters in the region in 2012.

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